1. Field of Invention
This invention relates to integrated circuits. Specifically, the present invention relates to systems for preventing or reducing leakage in synchronous digital systems during sleep mode.
2. Description of the Related Art
Integrated circuits are employed in various demanding applications including personal computers, cellular telephones, watches, and finite state machines. Such applications demand high-performance integrated circuits that exhibit minimal current leakage when idle or in sleep mode. Current leakage is particularly problematic in mobile applications, such as cellular telephones, laptops, and personal digital assistants, where long battery life is desirable.
These applications often employ synchronous digital systems implemented via integrated circuits. Synchronous digital systems employ synchronizing clocks to properly sequence circuit operations. Power consumption and performance of a synchronous digital system depends on the power consumption and performance of constituent components, such as latches. Latches are ubiquitous in many modern synchronous systems. Consequently, high-speed latches that exhibit minimal current leakage and associated power consumption are desirable.
To address leakage concerns, High Voltage Threshold transistors (HVT's) are often employed. An HVT requires a relatively high voltage at the transistor gate to turn on the transistor to enable a conduction path through the transistor. When an HVT is off, little or no current flows through the transistor. Consequently, HVT's exhibit minimal current leakage. Unfortunately, HVT's turn on relatively slowly. Consequently, latches employing primarily HVT's exhibit good leakage characteristics but are typically slow, which reduces the performance of the entire synchronous digital system.
To address performance concerns, Low Voltage Threshold (LVT) transistors are often employed. LVT's turn on relatively quickly with minimal gate voltage. However, LVT's are often leaky. Consequently, latches and associated systems employing LVT's are often leaky.
A tradeoff exists between low leakage and high performance. Generally, high performance latches exhibit high current leakage during sleep mode. Low performance latches exhibit low leakage during sleep mode.
To achieve both acceptable performance and low leakage, engineers have developed hybrid latches that employ a combination of selectively placed HVT's and LVT's. Unfortunately, to achieve acceptable performance and leakage characteristics, these hybrid latches require that the synchronizing clock sleeps low such that clock is low when the latch is in sleep mode or that the synchronizing clock sleeps high such that the clock is high when the latch is in sleep mode.
If the hybrid latch is designed so that the clock sleeps high, an HVT pass gate is typically positioned before an LVT pass gate in the data path. The resulting latch exhibits an undesirably lengthy setup time and a short transition delay. The setup time is the time delay between stabilization of an input and the triggering edge of the synchronizing clock. The transition delay is the time interval between the triggering edge of the clock and the stabilization of the latch output. When referring to a D flip-flop latch, also called a delay flip-flop or a DQ flip-flop, the transition delay is often called the clock-to-Q delay, where Q represents the latch output.
The lengthy setup time results from the slow HVT pass gate. The clock signal that controls the LVT pass gate must wait for the input to arrive at the LVT pass gate via the slow HVT pass gate, yielding a long setup time. The minimal transition delay results from the fast LVT pass gate, which minimizes the delay between the input of the LVT pass gate and the output of the latch.
If the hybrid latch is designed so that the clock sleeps low, an LVT pass gate is typically positioned before the HVT pass gate in the data path. The resulting latch exhibits a short setup time and an undesirably lengthy transition delay. The short setup time results from the fast LVT pass gate. The lengthy transition delay results from the slow HVT pass gate.
Conventionally, a tradeoff exists between setup time and transition delay. Conventional hybrid latches require that the clock either sleep high or low, causing a lengthy setup time or transition delay, respectively. Furthermore, the requirement that the clock either sleep high or low limits the applicability of these latches to certain applications not requiring latches to selectively sleep high and/or low.
Hence, a need exists in the art for a system that minimizes leakage in integrated circuits during sleep mode without compromising performance. There exist a further need for an associated high-performance latch that can selectively sleep high or low; exhibits both minimal setup time and transition delay; and that minimizes current leakage during sleep mode.